A couple of ACS papers

Two recent papers in the ASAP section of Nano Letters caught my eye.

The first is van der Molen et al., "Light-controlled conductance switching of ordered metal−molecule−metal devices". I've written a blurb about this for the ACS that will eventually show up here. The Schönenberger group has been working for a while on an approach for measuring molecular conductances that is based on networks of metal nanoparticles linked by molecules of interest. The idea is to take metal nanoparticles and form an ordered array of them with neighbors linked by molecules of interest covalently bound to the particle surfaces. The conductance of the array tells you something about the conductance of the particle-molecule-particle junctions. This is simple in concept and extremely challenging in execution, in part because when the metal nanoparticles are made by chemical means they are already coated with some kind of surfactant molecules to keep them suspended in solution. Performing the linking chemistry in a nice way and ending up with an ordered array of particles rather than a blob of goo requires skill and expertise. These folks have now made arrays incorporating molecules that can change reversibly change their structure upon exposure to light of the appropriate wavelength. The structural changes show up in photo-driven changes in the array conductance.

The second is Ryu et al., "CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes". Lots of people talk a good game about trying to make large-scale integrated circuits using nanotubes, but only a couple of groups have made serious progress. This paper by Chongwu Zhou's group shows that they can take arrays of tubes (grown by chemical vapor deposition on quartz or sapphire substrates), transfer them to Si wafers via a clever method involving gold, pattern the tubes, put down electrodes for devices, burn out the metallic tubes, and dope the semiconductor tubes chemically to do either p or n-type conduction. They are also working on fault-tolerant architectures to deal with the fact that each transistor (which in this case incorporates an ensemble of tubes) has slightly different characteristics.