One big selling point of solid-state quantum computing platforms is the notion of
scalability. The semiconductor industry has spent billions of dollars and millions of person-hours developing the capability of fabricating tens of billions of nanoscale electronic components in parallel with
remarkable reliability. Surely it's not crazy to think that this will be the key to creating large numbers of functioning qubits as well.
Like many ideas that look plausible at first glance, this becomes very complicated under greater scrutiny. Many of the approaches that people have in mind for solid-state quantum computing are not necessarily compatible with the
CMOS manufacturing processes that produced the chips powering the computer you're currently using. Virtually all of the university groups working on these systems use university-type fabrication methods - electron beam lithography for patterning, lift-off processing, etc. In contrast, industrial chip makers use very different processes: elaborate immersion photolithography, subtractive patterning, and a whole host of clever tricks that have driven forward the mass production of silicon nanoelectronics. The situation gets even worse in terms of materials development if one considers attempts to use
more exotic systems. The most reasonable quantum computing platform to approach first, if one is worried about industrial compatibility is probably using
spins in gate-defined quantum dots in silicon.
A team from
Delft and Intel has done just that, as shown in
this preprint. They successfully demonstrate basic single-qubit effects like
Rabi oscillations in single spins in quantum dots (single-electron transistors) defined in
FinFETs, which they have patterned across a full 300 mm wafer (!) of isotopically pure 28Si (to avoid decoherence issues associated with nuclear spin). They present data (which I have not read carefully) about how reproducible the properties of the single-electron transistors are across the wafer.
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The contrast between Si quantum devices produced through university fab(top) and elite industrial fab (bottom). |
I think the figure here from their paper's supplementary material really shows the point in terms of fabrication methods. At the top is a cross-sectional TEM image of a chain of quantum dot devices, where the bright lumpy features are the defining metal gates that were patterned by e-beam lithography and deposited by lift-off processing. In contrast, at the bottom is a cross-sectional TEM of the nominally equivalent industrially made device. Behold the result of the accumulation of decades of technique and experience.
Of course, they were able to do this because Intel decided that it was worth it to invest in developing the special purpose masks and the process flow necessary. Universities ordinarily don't have access to the equipment or the specialists able to do this work. This makes me wonder again, as I have several times over the years, whether it would have been worthwhile for DOE or NSF to have set up (perhaps with Intel or IBM as a public-private partnership) some fabrication hub that would actually give the broader university research community access to these capabilities and this expertise. It would be very expensive, but it might have pushed technology farther ahead than having several "nanocenters" that don't necessarily have technology much different than what is available at the top two dozen university cleanrooms.