Saturday, October 08, 2016

What do LBL's 1 nm transistors mean?

In the spirit of this post, it seems like it would be a good idea to write something about this paper (accompanying LBL press release), particularly when popular sites are going a bit overboard with their headlines ("The world's smallest transistor is 1nm long, physics be damned").  (I discuss most of the background in my book, if you're interested.)

What is a (field effect) transistor and how does it work?  A transistor is an electronic switch, the essential building block of modern digital electronics.  A field-effect transistor (FET) has three terminals - a "source" (an input), a "drain" (an output) on either side of a semiconductor "channel", and a "gate" (a control knob).  If you think of electrical current like fluid flow, this is like a pipe with an inlet, and outlet, and a valve in the middle, and the gate controls the valve.  In a "depletion mode" FET, the gate electrode repels away charges in the channel to turn off current between the source and drain.  In an "accumulation mode" FET, the gate attracts mobile charges into the channel to turn on current between the source and drain.   Bottom line:  the gate uses the electrostatic interaction with charges to control current in the channel.  There has to be a thin insulating layer between the gate and the channel to keep current from "leaking" from the gate.   People have had to get very clever in their geometric designs to maximize the influence of the gate on the charges in the channel.

What's the big deal about making smaller transistors?  We've gotten where we are by cramming more devices on a chip at an absurdly increasing rate, by making transistors smaller and smaller.  One key length scale is the separation between source and drain electrode.  If that separation is too small, there are at least two issues:  Current can leak from source to drain even when the device is supposed to be off because the charge can tunnel; and because of the way electric fields actually work, it is increasingly difficult to come up with a geometry where the gate electrode can efficiently (that is, with a small swing in voltage, to minimize power) turn the FET off and on.

What did the LBL team do?  The investigators built a very technically impressive device, using atomically thin MoS2 as the semiconductor layer, source and drain electrodes separated by only seven nm or so, a ZrO2 dielectric layer only a couple of nm thick, and using an individual metallic carbon nanotube (about 1 nm in diameter) as the gate electrode.  The resulting device functions quite well as a transistor, which is pretty damn cool, considering the constraints involved.   This fabrication is a tour de force piece of work.

Does this device really defy physics in some way, as implied by the headline on that news article?  No.  That headline alludes to the issue of direct tunneling between source and drain, and a sense that this is expected to be a problem in silicon devices below the 5 nm node (where that number is not the actual physical length of the channel).   This device acts as expected by physics - indeed, the authors simulate the performance and the results agree very nicely with experiment.

If you read the actual LBL press release, you'll see that the authors are very careful to point out that this is a proof-of-concept device.  It is exceedingly unlikely (in my opinion, completely not going to happen) that we will have chips with billions of MoS2 transistors with nanotube gates - the Si industry is incredibly conservative about adopting new materials.  If I had to bet, I'd say it's going to be Si and Si/Ge all the way down.   (You will very likely need to go away from Si if you want to see this kind of performance at such length scales, though.)   Still, this work does show that with proper fabrication and electrostatic design, you can make some really tiny transistors that work very well!


7 comments:

Anonymous said...

Nifty device, but the length that really matters for transistors is the channel length, not the gate length. If you look at their results, the channel length in the off state is still of the order of 5nm or even more - they cook up some "LEFF" measurement of the channel length ~ 3.9nm, which happens to be a bit less than 5nm - but in the end the gateable part of the material is even much longer than that. As you point out, Doug, there is no physics miracle here.

If an engineer wanted integrate this device into a processor, he or she would need to self-align the source and drain contacts to the nanotube, with some spacer to limit tunneling leakage current, and the source and drain would still end up having to be separated by more than 5nm.

"1nm" in the title is a bit misleading, IMHO. A 5nm-wide nanotube or nanowire for the gate would do just as good of a job, with no loss in scaling dimension, as long as the channel is made out of an ultrathin conductive material.

Technologically speaking, I think you also need excellent control of the nanotube species in order to get identical and predictable threshold voltages (this is the age-old problem with CNTs).

Douglas Natelson said...

Anon, I agree with you. An eventual scalable way to do this would (i) use Si or SiGe as the channel, because CMOS cost structure makes essentially everything else noncompetitive out of the gate economically; (ii) use some kind of patterned metallic silicide as the gate electrode, because there is no way they're really going to put metallic or very tiny bandgap nanotubes down as gates - perhaps something like these: http://scitation.aip.org/content/aip/journal/jap/91/5/10.1063/1.1428807 but that's a huge stretch; (iii) use some kind of metal or metallic silicide source and drain electrodes, because doping won't work with this kind of spatial resolution and would lead to huge variations in contact resistance and threshold voltage; (iv) probably use some finFET or other multigate configuration to improve gate coupling.

Anonymous said...

Also, the effective channel length, i.e. the length of the active region may only be about 7 nm (since the global back gate turns the whole thing on or off, so the tube just has to switch a small region from insulating to conducting), but the separation between the source and drain electrodes is almost a micron (fig 1c), which is pretty huge. I dunno, I am a bit less impressed by this paper as I feel like I have seen similar work before that was just hyped less.

Anonymous said...

The most interesting aspect of this transistor, from the point of view of a development engineer, is actually that the small gate will have a lower capacitance to the source and drain contacts. S/D contacts will have to be drawn very close to the channel in a manufacturable device, and one of the biggest issues with scaling nowadays is that the proximity of source and drain to the gate causes a large stray capacitance, which slows down transistor switching. The gate nowadays also needs to be relatively tall (~100nm!), in order to fill it with some low-resistance metal, and this also increases capacitance. So a highly conductive nanotube is a much better gate in that respect, if it can be made reproducibly and positioned precisely.

What I don't know is whether this is the first work that reports on a MOS device gated by a nanotube (I am *not* referring to a "CNT FET"). My guess is they are probably not the first.

(Anon #1)

Anonymous said...

Anon#1 again here. One more comment: what determines the actual channel length here is simply the oxide thickness. If the oxide is 5nm thick, the channel will be ~5nm long; a 2nm channel could simply be obtained by depositing a 2nm-thin oxide, etc.

It's interesting that the article shows no data for the thin-oxide, short-channel devices, presumably because they have a bad ION/IOFF ratio (as they should).

To respond to Anon#2's comment: the authors drew source and drain contacts a couple of microns apart because this is a proof-of-concept device; it should be possible, in principle, to bring those contacts much closer to the channel, by some self-alignment technique. For example, you could revert the process and lay the nanotube last, then coat it with some thin insulator (a half-"sheath") than only deposits on the nanotube, then deposit the S/D metal, and lift it off the nanotube by etching its oxide sheath, thereby separating the source and drain contact areas. Done!

Anonymous said...

I saw tens of people shared this news/paper on LinkedIn. Our Assoc. Dean for research even sent me an email about this. I am sorry but this is just another great PR of a big shot at a big university.

Just a short story of mine. Five years ago I hired a postdoc, who told me that he was an "expert" of graphene synthesize. I asked him to fabricate a simple design. He asked for four weeks. I was like "what the heck do you need a month to fabricate such a simple device". He was like "i can fabricate it in 2 hours but finding the one which works takes a month"

Anonymous said...

Funny story. Even though it is currently very tedious to make devices out of graphene and other layered materials, their promise is predicated on the hope that, one day, we will be able to grow them as a film of controlled thickness on a large wafer.