In the spirit of this post, it seems like it would be a good idea to write something about this paper (accompanying LBL press release), particularly when popular sites are going a bit overboard with their headlines ("The world's smallest transistor is 1nm long, physics be damned"). (I discuss most of the background in my book, if you're interested.)
What is a (field effect) transistor and how does it work? A transistor is an electronic switch, the essential building block of modern digital electronics. A field-effect transistor (FET) has three terminals - a "source" (an input), a "drain" (an output) on either side of a semiconductor "channel", and a "gate" (a control knob). If you think of electrical current like fluid flow, this is like a pipe with an inlet, and outlet, and a valve in the middle, and the gate controls the valve. In a "depletion mode" FET, the gate electrode repels away charges in the channel to turn off current between the source and drain. In an "accumulation mode" FET, the gate attracts mobile charges into the channel to turn on current between the source and drain. Bottom line: the gate uses the electrostatic interaction with charges to control current in the channel. There has to be a thin insulating layer between the gate and the channel to keep current from "leaking" from the gate. People have had to get very clever in their geometric designs to maximize the influence of the gate on the charges in the channel.
What's the big deal about making smaller transistors? We've gotten where we are by cramming more devices on a chip at an absurdly increasing rate, by making transistors smaller and smaller. One key length scale is the separation between source and drain electrode. If that separation is too small, there are at least two issues: Current can leak from source to drain even when the device is supposed to be off because the charge can tunnel; and because of the way electric fields actually work, it is increasingly difficult to come up with a geometry where the gate electrode can efficiently (that is, with a small swing in voltage, to minimize power) turn the FET off and on.
What did the LBL team do? The investigators built a very technically impressive device, using atomically thin MoS2 as the semiconductor layer, source and drain electrodes separated by only seven nm or so, a ZrO2 dielectric layer only a couple of nm thick, and using an individual metallic carbon nanotube (about 1 nm in diameter) as the gate electrode. The resulting device functions quite well as a transistor, which is pretty damn cool, considering the constraints involved. This fabrication is a tour de force piece of work.
Does this device really defy physics in some way, as implied by the headline on that news article? No. That headline alludes to the issue of direct tunneling between source and drain, and a sense that this is expected to be a problem in silicon devices below the 5 nm node (where that number is not the actual physical length of the channel). This device acts as expected by physics - indeed, the authors simulate the performance and the results agree very nicely with experiment.
If you read the actual LBL press release, you'll see that the authors are very careful to point out that this is a proof-of-concept device. It is exceedingly unlikely (in my opinion, completely not going to happen) that we will have chips with billions of MoS2 transistors with nanotube gates - the Si industry is incredibly conservative about adopting new materials. If I had to bet, I'd say it's going to be Si and Si/Ge all the way down. (You will very likely need to go away from Si if you want to see this kind of performance at such length scales, though.) Still, this work does show that with proper fabrication and electrostatic design, you can make some really tiny transistors that work very well!