Like many ideas that look plausible at first glance, this becomes very complicated under greater scrutiny. Many of the approaches that people have in mind for solid-state quantum computing are not necessarily compatible with the CMOS manufacturing processes that produced the chips powering the computer you're currently using. Virtually all of the university groups working on these systems use university-type fabrication methods - electron beam lithography for patterning, lift-off processing, etc. In contrast, industrial chip makers use very different processes: elaborate immersion photolithography, subtractive patterning, and a whole host of clever tricks that have driven forward the mass production of silicon nanoelectronics. The situation gets even worse in terms of materials development if one considers attempts to use more exotic systems. The most reasonable quantum computing platform to approach first, if one is worried about industrial compatibility is probably using spins in gate-defined quantum dots in silicon.
A team from Delft and Intel has done just that, as shown in this preprint. They successfully demonstrate basic single-qubit effects like Rabi oscillations in single spins in quantum dots (single-electron transistors) defined in FinFETs, which they have patterned across a full 300 mm wafer (!) of isotopically pure 28Si (to avoid decoherence issues associated with nuclear spin). They present data (which I have not read carefully) about how reproducible the properties of the single-electron transistors are across the wafer.
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| The contrast between Si quantum devices produced through university fab(top) and elite industrial fab (bottom). |
I think the figure here from their paper's supplementary material really shows the point in terms of fabrication methods. At the top is a cross-sectional TEM image of a chain of quantum dot devices, where the bright lumpy features are the defining metal gates that were patterned by e-beam lithography and deposited by lift-off processing. In contrast, at the bottom is a cross-sectional TEM of the nominally equivalent industrially made device. Behold the result of the accumulation of decades of technique and experience.
Of course, they were able to do this because Intel decided that it was worth it to invest in developing the special purpose masks and the process flow necessary. Universities ordinarily don't have access to the equipment or the specialists able to do this work. This makes me wonder again, as I have several times over the years, whether it would have been worthwhile for DOE or NSF to have set up (perhaps with Intel or IBM as a public-private partnership) some fabrication hub that would actually give the broader university research community access to these capabilities and this expertise. It would be very expensive, but it might have pushed technology farther ahead than having several "nanocenters" that don't necessarily have technology much different than what is available at the top two dozen university cleanrooms.
6 comments:
Might still happen, Doug. Drop me a line.
Wasn't there a massive joint academic-industry 300mm fab built in Albany, NY with SUNY/Intel/IBM/...? What ever happened to that? If it didn't succeed the way you're proposing Doug, what lessons can we learn from it?
There is indeed a giant nanofab in Albany: https://sunypoly.edu/research/albany-nanotech-complex.html. I toured there about 15 years ago, and it's extremely impressive. They had one of the first full EUV-litho machines for 300 mm wafers.
Others are undoubtedly more knowledgable than I am. My impression had been that the really serious infrastructure was being used by, e.g., IBM (replacing their Fishkill facility) and others in industry for prototyping, so it was not really open for academic use. There definitely was not a way to work with mask designers, etc., for academic projects, and the materials limitations were extremely stringent because of the need to be able to produce state-of-the-art CMOS. That was a long time ago, though. Perhaps someone more knowledgable can chime in.
Prof. Natelson, isn't IMEC what you have in mind? You have world class resources there (like Albany) and you have world class research going on there (more so than Albany). The other thought I have is that in Europe, you have PhD students doing research at companies. For example, there are PhD students doing their PhDs working out of Infineon's Technology Development labs in Villach, Austria. There were really good papers that those students published on GaN reliability while working at Villach. Why can't we have PhD students working out of Intel or IBM for example? It would help IBM develop talent and we would also get better research out as well.
Anon@11:45 - yes, IMEC is a lot closer to what I have in mind, though I don't know how easy it would be for, say, a non-electrical engineer researcher at the Catholic University of Leuven to be able to work with 15 nm process engineers on mask and structure design. Regarding PhD students working for companies in the US, this does happen at some rate (and it used to be more prevalent), though I believe many of those students are usually doing research that is very product-directed. The general decline of long-term industrial research hurts there.
I was curious about the scale of these images. The final article published in Nature Electronics includes a scale bar which shows that the width of the lower image is about 520 nm. Unfortunately it seems that this specific image comparing university/industrial fabs is only in the preprint! Too bad that it was removed.
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