Thursday, July 18, 2013
Printing at the 180 nm scale??
I stumbled across this post, where it is asserted (with no link, and my google-fu is inadequate) that some group or collaboration at Berkeley is working on the ability to make 180 nm critical dimension transistors via printing (and therefore over really large areas, rather than only on dinner-plate-sized Si wafers). Can a reader out there point me to who is really doing this, or is this a case of a press office distorting things (e.g., taking a layer thickness and claiming it's a lateral feature size)?
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8 comments:
I'm guessing it's the work of Vivek Subramanian's group, though I suspect the claims in that press release are exaggerated.
Grumpy, could be. I met and spoke w/ Vivek back when I was doing more organic electronics work. He did a great job conveying what a challenging task it is to use inkjet-style techniques to print electronic materials. Still, I know of no printing technology that allows 180 nm lateral resolution. That would be fantastic, though - imagine a printing technology that can deliver more than 10^5 dpi over large areas!
I had the article which was based on the EETimes coverage of the keynote by Janusz Bryzek of Fairchild Semiconductor at Semicon West where Janusz mentioned -
UC Berkeley is now developing printed transistors at 180nm. The technology could deliver chips costing $25 a square meter, not the $25,000 per square meter of current processes, again a huge cost reduction that is mind boggling.
Here is what I could find.
http://nextbigfuture.com/2013/07/technical-publications-related-to.html
yeah that would be pretty awesome. Hopefully an expert will weigh in on how far away we are.
Professor Natelson,
I sent you an email to ask for some help on June 29, but have not heard back from you about it. I wonder whether it might have been filtered out as spam. Can you check your email and see if you can find it? If you cannot afford the time, I can understand. Thanks!
Best regards,
Xiuwen
Xiuwen, please re-send; I can't find anything....
Professor Natelson,
I resent the email just now. Thanks!
Best regards,
Xiuwen
The solution of the mystery is about as complex as the "Slylok Fox" series - modern journalism which repeats rumors and distorts them like the old telephone game.
The words reported by David Blaza appear in one slide of Janus Bryzek's introductory talk at the Semicon West symposium. The UMass program one can actually find out about (it is headed by James Watkins); note that not a word is said about the size of the transistors that would be available in this $25/sqm product (which of course is a quite reasonable cost for a printed product; $0.25/sqm is the correct ballpark for normal print).
Regarding the UC Berkeley program, the journalist should inquire as to what is meant by "print". With a little care he might have noted that there exists such a thing as "nanoimprint lithography" which can make features down to 20 nm. This is not the same as what the average reader imagines when he or she sees the word "print". Lest you think that no one would use such a broad brush, recall that IDTechEx has not infrequently classified vacuum-deposited OLEDs as "printed electronics" (they do note their redefinition in the fine print of a footnote, but not in the headlines). Nano e-Print (now PragmatIC Printing) is certainly considered a "printed electronics" company by IDTechEx as well as others.
There is a company in Japan which has developed an inkjet printer which can make 0.5 micron lines (that is their "spearhead" accomplishment, not what they assert to be realistic for normal use). But even that is far from being useful for mass produced transistor devices, and could not in any case compete with silicon (even of the same feature size). There are small matters of overlay accuracy, cost per unit throughput, and the performance of the devices...
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