Thursday, July 18, 2013
Printing at the 180 nm scale??
I stumbled across this post, where it is asserted (with no link, and my google-fu is inadequate) that some group or collaboration at Berkeley is working on the ability to make 180 nm critical dimension transistors via printing (and therefore over really large areas, rather than only on dinner-plate-sized Si wafers). Can a reader out there point me to who is really doing this, or is this a case of a press office distorting things (e.g., taking a layer thickness and claiming it's a lateral feature size)?
Posted by Douglas Natelson at 3:17 PM