Friday, June 26, 2026

Some science/tech items - scrolls, nanostacks, and beyond

 Some brief science and technology items heading into the weekend:

  • IBM has reported making prototype chips for the "0.7 nm node".   As always, one should not interpret that size scale literally, since the effective diameter of a single silicon atom is around 0.2 nm.  The basic building block of their architecture here is the nanostack, which is a limiting case, somewhat 3D-integrated version of their nanosheet "gate all around" field effect transistors.  The fact that these structures can be made at this scale, reliably and en masse, is just phenomenal.  
     


  • I'd written previously about the Vesuvius Challenge, the attempt to use a combination of x-ray tomographic imaging and machine learning to read the carbonized ancient Roman scrolls found in a villa in Herculaneum, where they had been buried by the pyroclastic flow from the eruption in 79CE.  Well, they've managed to read a complete scroll - here's the preprint.  Very cool, and the hope is that among those scrolls might be books believed lost to history.
  • At the beginning of the month, Microsoft unveiled the next iteration of their approach to implementing topological qubits based on superconductor/semiconductor hybrid devices, as described here.  The relevant preprint is this one.  Some reporting on this is here.  This week, Nature published a comment on the prior work as well as the reply.  
  • There has been an explosion of research in recent years about trying to use electromagnetic cavities to tune the physical properties of condensed matter systems.  I'd discussed this here.  In the last couple of weeks, this preprint appeared, reporting that placing few-layer NbSe2 in an appropriate (THz) cavity can increase the superconducting transition temperature from 3.02 K to 3.41 K.  A 13% increase in \(T_{\mathrm{c}}\) is certainly interesting.
  • The incoming president of the National Academy of Sciences has a nice statement in Science.  The key passage for me:  "By its charter, the Academy is nonpartisan and neither a progressive organization nor a conservative one. It is a scientific body that follows the evidence wherever it leads, even when the destination might be unwelcome. In heated and polarized discourse, it is the Academy’s obligation to be the most careful and trustworthy voice. But rigorous science that arrives too late, or speaks too quietly, serves no one."  

8 comments:

  1. Anonymous12:40 PM

    Doug, the IBM nanostack device cannot yet be made reliably and en masse. It is a demonstration device produced by a research lab. Also, Imec, Intel, Tsmc, and Samsung have already produced similar stacked devices (called "CFET" in the field), with variations in the process. IBM is actually coming a bit late to party. Where IBM stands out is in the strength of their marketing department. Also, they have staggered the top and bottom devices, which is indeed one of the innovations.

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    1. Anonymous11:06 PM

      They also used different Si orientation wafers for NMOS and PMOS and did very precise wafer bonding to facilitate circuit formation which is also a key feature.

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    2. Anonymous6:25 AM

      Intel is also using different Si orientations (others are likely doing the same)... and precise wafer bonding is not actually needed to transfer the Si films, so I'm not sure why this is being reported. But litho exposures for the 2nd transistor surely have to align to the lower device (which is true for all sequential CFET processes). To be fair to IBM, it's O.K. to come a couple of years behind the others... after all, the CFET/nanostack won't come to manufacturing for another ten years at the very least, so there's still plenty of time.

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    3. Thanks to all for the insightful comments. I appreciate having knowledgable readers, as it's tough to follow the details if one does not work directly in the area and attend/read the relevant device-related conferences/journals.

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    4. Anonymous9:50 AM

      Anonymous6:25 AM, wouldn’t precise bonding be required to wire together the PMOS and NMOS wafers together to make sure that they are making the correct inverter circuits?

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    5. Anonymous2:44 PM

      Precise bonding is not needed in IBM's case, because what they are doing is a "sequential" process: they make the first transistor (say, PMOS) on a wafer, then transfer a bare, crystalline, semiconductor film on top of the PMOS transistor (this is a bonding step, but just a film transfer), then pattern the second transistor (NMOS) out of this transferred film. The top transistor has to be registered to the bottom one, but this is a standard alignment procedure in the lithography process of the top transistor. So no "aligned bonding" is done in this process.

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    6. Anonymous2:50 PM

      Doug you are welcome! And I appreciate your posts summarizing recent news of interest in our field, ranging from the fundamental to the more applied.

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  2. Anonymous12:45 PM

    On the Microsoft qubit: for those who didn't click the link to the comment, this topological qubit is complete BS, as is sadly too often the case in the quantum computing field. It is most likely explained by some trivial state. What can you do? Big egos + big money + quantum obfuscation = pseudo-science.

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